Microchip Technology /ATSAMV70Q20 /MPU /RASR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RASR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0SIZE0SRD0 (B)B0 (C)C0 (S)S0TEX0AP0 (XN)XN

Description

MPU Region Attribute and Size Register

Fields

ENABLE

Region enable bit.

SIZE

Specifies the size of the MPU protection region.

SRD

Subregion disable bits.

B

MPU access permission attributes.

C

MPU access permission attributes.

S

Shareable bit.

TEX

MPU access permission attributes.

AP

Access permission field.

XN

Instruction access disable bit.

Links

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